View CS4630_1981247.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

preliminary product information this document contains information for a new product. cirrus logic reserves the right to modify this product without notice. 1 copyright ? cirrus logic, inc. 1999 (all rights reserved) p.o. box 17847, austin, texas 78760 (512) 445 7222 fax: (512) 445 7581 http://www.cirrus.com CS4630 features l 420 mips slimd ? dsp architecture with increased internal memory for greater performance l hardware acceleration for microsoft directsound a and directsound3d a positional audio l sensaura? 3-d, 2 or 4 channel audio l eax? 1.0 enhanced environmental audio standard l unlimited-voice wavetable synthesis with effects including dls support l acoustic echo cancellation hardware acceleration for netmeeting ? l 10 band graphic equalization l high quality hardware sample rate conversion (90+ db dynamic range) l pc/pci, ddma, and crystalclear legacy support (ccls ? ) l pci 2.1 compliant pci interface l full duplex, 128 stream dma interface with hardware scatter/gather support l pci power management (d0 through d3 cold ), apm 1.2, and acpi 1.0 l power management event (pme#) generation within d0-d3 cold l dual ac 97 2.1 codec interface l asynchronous digital serial interface (zv port) l s/pdif digital input and output support for pcm and ac3 encoded 5.1 channel formats l directinput ? joystick and mpu- 401 midi in/out l 3.3 v / 2.5 v power supply (5 v tolerant i/o) l pc 98 and pc 99 compliant description the CS4630 is a high performance upgrade to the cs4624 pci audio accelerator. with support for legacy compatibility modes, the CS4630 enables real mode dos compatibility within pci-only audio subsystems. this device, combined with application and driver software, provides a complete system solution for hardware acceleration of microsofts directsound, directsound3d, directinput, and wavetable synthesis. wdm drivers provide support for both windows 98 a and windows 2000 a . the CS4630 is based on the cirrus logic crystalclear ? stream processor (sp) dsp core. the sp core is optimized for digital audio processing, and is powerful enough to handle complex signal processing tasks such as sensaura 3d, 4-channel output, and hardware wavetable synthesis. the sp core is supported by a bus mastering pci interface and a built-in dedicated dma engine with hardware scatter-gather support. these support functions ensure extremely efficient transfer of audio data streams to and from host-based memory buffers, providing a system solution with maximum performance and minimal host cpu loading. ordering information CS4630-cm 128-pin mqfp 14x20x2.85 mm nov 99 ds445pp1 crystalclear ? soundfusion a pci audio accelerator 28-stream dma controller with hardware scatter/gather mpu-401 midi interface pci interface joystick interface pc/pci & ccls legacy s/pdif in s/pdif out zv port program rom parameter ram slimd sp core sample ram program ram coefficient rom dual codec ac '97 2.1 interface async. serial port interface 1 egpio
CS4630 2 ds445pp1 table of contents 1. characteristics/specifications .................................................. 4 absolute maximum ratings ........................................................................................... 4 recommended operating conditions ....................................................................... 4 ac characteristics (pci signal pins only) .............................................................. 5 dc characteristics.......................................................................................................... 6 pci interface pins ............................................................................................................. 7 ac 97 serial interface timing ...................................................................................... 8 zv port timing................................................................................................................. .... 9 independent timing environment ............................................................................. 10 eeprom timing characteristics................................................................................ 11 2. overview ................................................................................................... 12 2.1 stream processor dsp core ........................................................................................... 13 2.2 legacy support ............................................................................................................ .... 13 3. system architectures ...................................................................... 14 4. host interface ...................................................................................... 15 4.1 pci bus transactions ...................................................................................................... .15 4.2 configuration space ....................................................................................................... .17 4.3 subsystem vendor id fields ........................................................................................... 19 4.4 dynamic config register ................................................................................................. 19 4.5 interrupt signal .......................................................................................................... ...... 19 5. serial port configurations ......................................................... 20 6. game port ................................................................................................. 22 6.1 midi port ................................................................................................................. ......... 22 6.2 joystick port ............................................................................................................. ........ 22 7. eeprom interface ................................................................................ 23 8. general purpose i/o pins .................................................................. 24 8.1 egpio ..................................................................................................................... ........ 24 9. zv port serial interface ................................................................ 24 contacting cirrus logic support for a complete listing of direct sales, distributor, and sales representative contacts, visit the cirrus logic web site at: http://www.cirrus.com/corporate/contacts/ ccls, slimd, and crystalclear are trademarks of cirrus logic, inc. directinput and directx are trademarks of microsoft corporation. directsound, directsound3d, windows 98 and windows 2000 are registered trademarks of microsoft corporation. eax is a trademark of creative technology, ltd. intel is a registered trademark of intel. netmeeting is a trademark of microsoft corporation. sensaura is a trademark of sensaura, inc. sound blaster pro is a trademark of creative technology, ltd. soundfusion is a registered trademark of cirrus logic, inc. all other names are trademarks, registered trademarks, or service marks of their respective companies. preliminary product information describes products which are in production, but for which full characterization data is not yet available. advance prod- uct information describes products which are in development and subject to development changes. cirrus logic, inc. has made bes t efforts to ensure that the information contained in this document is accurate and reliable. however, the information is subject to change without notice and is provided as is without warranty of any kind (express or implied). no responsibility is assumed by cirrus logic, inc. for the use of th is information, nor for infringements of patents or other rights of third parties. this document is the property of cirrus logic, inc. and implies no l icense under patents, copy- rights, trademarks, or trade secrets. no part of this publication may be copied, reproduced, stored in a retrieval system, or t ransmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of cirrus logic, inc. it ems from any cirrus logic website or disk may be printed for use by the user. however, no part of the printout or electronic files may be copied, r eproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of cirrus logic, inc.furthermore, no part of this publication may be used as a basis for manufacture or sale of any items witho ut the prior written consent of cirrus logic, inc. the names of products of cirrus logic, inc. or other vendors and suppliers appearing in this docu ment may be trade- marks or service marks of their respective owners which may be registered in some jurisdictions. a list of cirrus logic, inc. t rademarks and service marks can be found at http://www.cirrus.com.
CS4630 ds445pp1 3 10. consumer iec-958 digital interface (s/pdif) ...................... 24 11. pci power management .................................................................. 26 11.1 d0 state ................................................................................................................. ........ 26 11.2 dl state ................................................................................................................. ......... 26 11.3 d2 state ................................................................................................................. ........ 26 11.4 d3hot state .............................................................................................................. ...... 26 11.5 d3 cold state ................................................................................................................... 26 11.6 CS4630 pme# assertion ............................................................................................... 27 11.6.1 abitclk on ..................................................................................................... 27 11.6.2 abitclk off ................................................................................................... 27 11.7 on card vaux switching logic ...................................................................................... 27 12. pin description .......................................................................................................... ..... 29 12.1 pci interface ............................................................................................................ ...... 30 12.2 pci power management interface pins ........................................................................ 31 12.3 external interface pins .................................................................................................. 32 12.4 clock / miscellaneous .................................................................................................... 33 12.5 serial codec interface ................................................................................................... 34 12.6 zv port serial interface ................................................................................................. 35 12.7 consumer digital audio i/o (s/pdif) ............................................................................ 35 12.8 asynchronous serial interface and enhanced general purpose i/o ............................ 36 13. package outline ................................................................................ 37 list of figures figure 1. ac characteristics ................................................................................................... ... 5 figure 2. pci timing measurement conditions ......................................................................... 7 figure 3. ac 97 configuration timing diagram ........................................................................ 8 figure 4. zv port .............................................................................................................. ...... 9 figure 5. independent timing configuration ........................................................................... 10 figure 6. eeprom timing ...................................................................................................... 11 figure 7. CS4630 block diagram ............................................................................................ 12 figure 8. ac 97 codec interface ............................................................................................ 14 figure 9. portable docking station scenario ........................................................................... 14 figure 10. host interface base address registers .................................................................... 15 figure 11. ac 97 codec connection diagram .......................................................................... 20 figure 12. dual ac 97 codec connection diagram ................................................................. 21 figure 13. joystick logic ...................................................................................................... ..... 22 figure 14. external eeprom connection ................................................................................. 23 figure 15. eeprom read sequence ....................................................................................... 23 figure 16. zv port clocking format .......................................................................................... 24 figure 17. iec consumer interface implementation circuit ...................................................... 25 figure 18. optional fiber optic circuit ...................................................................................... 25 figure 19. on-card 3.3vaux switching logic ............................................................................ 28
CS4630 4 ds445pp1 1. characteristics/specifications absolute maximum ratings pcignd = cgnd = crygnd = 0 v, all voltages with respect to 0 v) notes: 1. includes all power generated by ac and/or dc output loading. 2. the power supply pins are at recommended maximum values. xtali & xtalo are at 3.6 v maximum. 3. at ambient temperatures above 70 c, total power dissipation must be limited to less than 0.4 watts. warning: operation beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. recommended operating conditions (pcignd = cgnd = crygnd = 0 v, all voltages with respect to 0 v) specifications are subject to change without notice. parameter symbol min typ max unit power supplies pcivdd cvdd cryvdd vdd5ref - - - - - - - - 4.6 tbd 4.6 5.5 v v v v total power dissipation (note 1) - - tbd w input current per pin, dc (except supply pins) - - tbd ma output current per pin, dc - - tbd ma input voltage (note 2) tbd - tbd v ambient temperature (power applied) (note 3) -45 - 85 c storage temperature -55 - 150 c parameter symbol min typ max unit power supplies pcivdd cvdd cryvdd vdd5ref 3 2.25 3 3/4.75 3.3 2.5 3.3 3.3/5 3.6 2.75 3.6 3.6/5.25 v v v v internal dsp frequency CS4630 - - 140 mhz operating ambient temperature t a 02570c
CS4630 ds445pp1 5 ac characteristics (pci signal pins only) (t a = 0 to 70 c; pcivdd = cryvdd = 3.3 v; cvdd = 2.5 v; vdd5ref = 5 v; pcignd = cgnd = crygnd = 0 v; logic 0 = 0 v, logic 1 = 3.3 v; reference levels = 1.4 v; unless otherwise noted; (note 4)) notes: 4. specifications guaranteed by characterization and not production testing. 5. refer to v/i curves in figure 1. specification does not apply to pciclk and rst# signals. switching current high specification does not apply to serr#, pme#, and inta# which are open drain outputs. 6. cumulative edge rate across specified range. rise slew rates do not apply to open drain outputs. 7. equation a: i oh = 11.9 * (vout - 5.25) * (vout + 2.45) for 3.3 v > vout > 3.1 v 8. equation b: i ol = 78.5 * vout * (4.4 - vout) for 0 v < vout < 0.71 v parameter symbol min max unit switching current high (note 5) 0 < vout < 1.4 1.4 < vout < 2.4 3.1 < vout < 3.3 i oh -44 - - - note 7 ma ma switching current low (note 5) vout > 2.2 2.2 > vout > 0.55 0.71 > vout > 0 i ol 95 vout/0.023 - - - note 8 ma ma low clamp current -5 < vin < -1 i cl -ma output rise slew rate 0.4 v - 2.4 v load (note 6) slewr 1 5 v/ns output fall slew rate 2.4 v - 0.4 v load (note 6) slewf 1 5 v/ns pull up equation a: 3.3 2.4 voltage 1.4 dc drive point ac drive point i = 11.9*(vout-5.25)*(vout+2.45) for 3.3v > vout > 3.1v oh test point -2 - 44 current (ma) - 176 pull down equation b: 3.3 2.2 0.55 voltage dc drive point i = 78.5*vout*(4.4-vout) for 0v < vout < 0.71v ol ac drive point test point 3, 6 95 380 current (ma) figure 1. ac characteristics
CS4630 6 ds445pp1 dc characteristics (t a = 0 to 70 c; pcivdd = cryvdd = 3.3 v; cvdd = 2.5 v; vdd5ref = 5 v; pcignd = cgnd = crygnd = 0 v; all voltages with respect to 0 v unless otherwise noted) notes: 9. the following signals are tested to 6 ma: frame#, trdy#, irdy#, devsel#, stop#, serr#, perr#, and inta#. all other pci interface signals are tested to 3 ma. 10. input leakage currents include hi-z output leakage for all bi-directional buffers with three-state outputs. 11. for open drain pins, high level output voltage is dependent on external pull-up used and number of attached gates. 12. all inputs that do not include internal pull-ups or pull-downs, must be externally driven for proper operation. if an input is not driven, it should be tied to power or ground, depending on the particular function. if an i/o pin is not driven and programmed as an input, it should be tied to power or ground through its own resistor. 13. typical values are given as average current with typical sp task execution and data streaming. current values vary dramatically based on the software running on the sp. 14. vih for the joystick position inputs (jacx jacy jbcx jbcy) is dependent on the joystick rate. parameter symbol min typ max unit pci interface signal pins high level input voltage v ih 2-5.75v low level input voltage v il -0.5 - 0.8 v high level output voltage iout = -2 ma v oh 2.4 - - v low level output voltage iout = 3 ma, 6 ma (note 9) v ol --0.55v high level leakage current vin = 2.7 v (note 10) i ih --70a low level leakage current vin = 0.5 v (note 10) i il ---70a non-pci interface signal pins (except xtalo) high level input voltage xtali other pins v ih 2.3 2 3.3 - 4.0 5.75 v v low level input voltage xtali other pins (note 14) v il -0.5 -0.5 0 - 0.8 0.8 v v high level output voltage iout = -3.5 ma (notes 11, 12) v oh 2.4 - - v low level output voltage iout = 3.5 ma (note 12) v ol --0.4v high level leakage current vin = 5.25 v (note 12) i ih --10a low level leakage current vin = 0 (note 12) i il ---10a parameter min typ max unit power supply pins (outputs unloaded) power supply current: vdd5ref pcivdd/cryvdd total( (notes 4,13) cvdd - - - tbd tbd tbd - tbd ma ma low power mode supply current - tbd - ma
CS4630 ds445pp1 7 pci interface pins (t a =0 to 70 c; pcivdd = cryvdd = 3.3 v; cvdd = 2.5 v; vdd5ref = 5 v; pcignd = cgnd = crygnd = 0 v; logic 0 = 0 v, logic 1 = 3.3 v; timing reference levels = 1.4 v) notes: 15. for active/float measurements, the hi-z or off state is when the total current delivered is less than or equal to the leakage current. specification is guaranteed by design, not production tested. 16. rst# is asserted and de-asserted asynchronously with respect to pciclk. 17. all output drivers are asynchronously floated when rst# is active. 18. req# and gnt# are point to point signals. all other pci signals are considered bused signals. parameter symbol min max unit pciclk cycle time t cyc 30 - ns pciclk high time t high 11 - ns pciclk low time t low 11 - ns pciclk to signal valid delay - bused signals (note 18) t val 211ns pciclk to signal valid delay - point to point (note 18) t val(p+p) 212ns float to active delay (note 15) t on 1-ns active to float delay (note 15) t off -28ns input set up time to pciclk - bused signals (note 18) t su 7-ns input set up time to pciclk - point to point (note 18) t su(p+p) 10, 12 - ns input hold time for pciclk t h 0-ns reset active time after pciclk stable (note 16) t rst-clk 100 - m s reset active to output float delay (notes 15, 16, 17) t rst-off -30ns pciclk t rst-clk rst# outputs hi-z inputs valid input t on t off t su t h outputs valid t val t rst-off figure 2. pci timing measurement conditions
CS4630 8 ds445pp1 ac 97 serial interface timing (t a = 0 to 70 c; pcivdd = cryvdd = 3.3 v; cvdd = 2.5 v;vdd5ref = 5 v; pcignd = cgnd = crygnd = 0 v; logic 0 = 0 v, logic 1 = 3.3 v; timing reference levels = 1.4 v; unless otherwise noted) parameter symbol min typ max unit abitclk/abitclk2 cycle time t aclk 78 81.4 - ns abitclk/abitclk2 rising to asdout/adsout2 valid t pd5 -1725ns asdin/asdin2 valid to abitclk/abitclk2 falling t s5 10 - - ns asdin/asdin2 hold after abitclk/abitclk2 falling t h5 5- -ns pciclk rising to arst#/arst2# valid t pd6 -10- ns pciclk t aclk pd5 h5 pd6 t t t t s5 figure 3. ac 97 configuration timing diagram abitclk/abitclk2 async/async2 asdout/asdout2 asdin/asdin2 arst#/arst2#
CS4630 ds445pp1 9 zv port timing parameter symbol min max unit zlrck delay after zsclk rising t slrd 2-ns zlrck setup before zsclk rising t slrs 32 - ns zsclk low period t sclk 22 - ns zsclk high period t sclkh 22 - ns zsdata setup to zsclk rising t sdlrs 32 - ns zsdata hold after zsclk rising t sdh 2-ns sclkh t slrs t slrd t sdlrs t sdh t sclkl t zsdata zsclk zlrck figure 4. zv port
CS4630 10 ds445pp1 independent timing environment (t a = 0 to 70 c; pcivdd = cryvdd = 3.3 v; cvdd = 2.5v; vdd5ref = 5 v; pcignd = cgnd = crygnd = 0 v; logic 0 = 0v, logic 1 = 3.3 v; timing reference levels = 1.4 v; xtali = 12.288 mhz; unless otherwise noted) parameter symbol min typ max units sclk output cycle time t sclk 312 326 - ns fsync output cycle time (@sclk falling edge) t fsync 20000 20833 - ns sclk falling to fsync transition t pd7 -45 2 45 ns lrclk output cycle time (@ sclk rising edge) t lrclk 20000 20833 - ns sclk rising to lrclk transition t pd8 -45 2 45 ns sclk falling to sdout/sdo2/sdo3 valid t pd9 - 2 45 ns sdin/sdin2 valid to sclk rising (si1f2-0: 010, si2f1-0: 00) t s6 30 - - ns sdin/sdin2 hold after sclk rising (si1f2-0: 010, si2f1-0: 00) t h6 30 - - ns sdin/sdin2 valid to sclk falling (si1f2-0: 011, si2f1-0: 01) t s7 30 - - ns sdin/sdin2 hold after sclk falling (si1f2-0: 011, si2f1-0: 01) t h7 30 - - ns xtal frequency 12.287 12.288 12.289 mhz xtali high time (note 4) 35 - - ns xtali low time (note 4) 35 - - ns mclk output frequency (note 4) 12.287 12.288 12.289 mhz sclk fsync lrclk sdout/sd02/sd03 sdin/sdin2 sdin/sdin2 t sclk t pd7 t fsync t lrclk t pd9 t pd8 15 0 15 0 t s6 17 16 0 17 16 0 19 18 0 19 18 0 t h6 t h7 t s7 figure 5. independent timing configuration
CS4630 ds445pp1 11 eeprom timing characteristics (t a = 0 to 70 c, pcivdd = cryvdd = 3.3 v; cvdd = 2.5v; vdd5ref = 5 v; pcignd = cgnd = crygnd = 0 v; logic 0 = 0 v, logic 1 = 3.3 v; timing reference levels = 1.4 v; pci clock frequency = 33 mhz; unless otherwise noted (note 4)) notes: 19. rise time on eedat is determined by the capacitance on the eedat line with all connected gates and the required external pull-up resistor. nominal values based on 4.7k and 22pf. parameter symbol min max units eeclk low to eedat data out valid t aa 07.0 m s start condition hold time t hd:sta 5.0 - m s eeclk low t leeclk 10 - m s eeclk high t heeclk 10 - m s start condition setup time (for a repeated start condition) t su:sta 5.0 - m s eedat in hold time t hd:dat 0- m s eedat in setup time t su:dat 250 - ns eedat/eeclk rise time (note 19) t r -1 m s eedat/eeclk fall time t f - 300 ns stop condition setup time t su:sto 5.0 - m s eedat out hold time t dh 0- m s eeclk eedat (in) eedat (out) t f t r t su:sta t hd:sta t hd:dat t su:dat t su:sto t aa t dh t heeclk t leeclk eedat (out) figure 6. eeprom timing
CS4630 12 ds445pp1 2. overview the CS4630 is a high performance audio accelera- tor dsp for the pci bus. this device, combined with application and driver software, provides a complete system solution for cost effective acceler- ation of microsofts directsound, direct sound3d, directinput, midi playback via wavetable synthesis with reverberation and chorus effects processing, and more. the following fea- tures can be enabled via updated device driver: ? primary ac 97 interface now 2.1 compatible ? 2nd ac 97 codec support ? increased on-board memory for enhanced algo- rithm execution and greater concurrency ? 128 dma streams supported ? pci power management event support(d0- d3 cold ) ? support for wake-up event via ac 97 2.1 link there are three main functional blocks within the CS4630: the stream processor, the pci interface, and the dma engine. a block diagram of the CS4630 device is shown in figure 7. the stream processor (sp) is a high speed custom digital sig- nal processor (dsp) core specifically designed for audio signal processing. this extremely powerful dsp core is capable of running complex algorithms and a number of different signal processing algo- rithms simultaneously. this high concurrency capa- bility is valuable for applications such as immersive 3d games, which may play a number of directsound streams, a number of directsound3d streams, and a midi music sequence simultaneously. separate ram memories are included on-chip for the sp program code (program ram), param- eter data (parameter ram), and audio sample data (sample ram). two rom memories store coefficients for sample rate conversion and audio decompression algorithms (coefficient rom) and common algorithm code (program rom). the ram-based dsp architecture of the cs46 30 ensures maximum system flexibility. the software function/feature mix can be adapted to meet the re- quirements of a variety of different applications, such as directx ? games, dvd movie playback, or dos applications. this ram-based architecture also provides a means for future system upgrades, figure 7. CS4630 block diagram 28-stream dma controller with hardware scatter/gather mpu-401 midi interface pci interface joystick interface pc/pci & ccls legacy s/pdif in s/pdif out zv port program rom parameter ram slimd sp core sample ram program ram coefficient rom dual codec ac '97 2.1 interface async. serial port interface 1 egpio
CS4630 ds445pp1 13 allowing the addition of new or upgraded function- ality through software updates. the CS4630 provides an extremely efficient bus mastering interface to the pci bus. the pci inter- face function allows economical burst mode trans- fers of audio data between host system memory buffers and the CS4630 device. program code and parameter data are also transferred to the CS4630 over the pci interface. the dma engine provides dedicated hardware to manage transfer of up to 128 concurrent audio/data streams to and from host memory buffers. the dma engine provides hardware scatter-gather support, allowing simple buffer allocation and management. this implementation improves sys- tem efficiency by minimizing the number of host interrupts. the CS4630 supports a variety of audio i/o config- urations including a single cs4297/97a/98/99 crystalclear ac 97 codec or dual cs4297/97a/98/99 codecs where the second codec is used to support 4-channel audio or resides in a portables docking station. the systems flexibility is further enhanced by the inclusion of a bi-direc- tional serial midi port, a joystick port, a hardware volume control interface, a zv port interface, and a serial data port which allows connection of an op- tional external eeprom device. 2.1 stream processor dsp core the CS4630 stream processor (sp) is a custom dsp core design which is optimized for processing and synthesizing digital audio data streams. the sp features a somewhat long instruction multiple data (slimd) modified dual harvard architecture. the device uses a 40-bit instruction word and oper- ates on 32-bit data words. the sp includes two multiply-accumulate (mac) blocks and one 16- bit arithmetic and logic unit (alu). the sp core is conservatively rated at 420 million instructions per second (420 mips) when running at an 140 mhz internal clock speed. the mac units perform dual 20-bit by 16-bit multiplies and have 40-bit ac- cumulators, providing higher quality than typical 16-bit dsp architectures. a programmable phase locked loop (pll) circuit generates the high frequency internal sp clock from a lower frequency input clock. the input to the pll may be from a crystal oscillator circuit or the serial port clock abitclk/sclk. clock con- trol circuitry allows gating of clocks to various in- ternal functional blocks to conserve power during power conservation modes, as well as during nor- mal modes of operation when no tasks are being executed. 2.2 legacy support legacy games are supported by crystalclear leg- acy support (ccls), ddma, or pc/pci interface. in both motherboard and add-in card designs, ccls and ddma provide support for legacy games by providing a hardware interface that sup- ports a sound blaster pro ? compatible interface, as well as support for fm, mpu-401, and joystick in- terfaces. these hardware interfaces provide pci- only games compatibility for real-mode dos and windows dos box support. for motherboard designs, pc/pci can be used by connecting the pcgnt# and pcreq# pins to the appropriate pins on the south bridge motherboard chip. the pc/pci interface is compliant with in- tels pc/pci spec. (version 1.2). the bios must enable the pc/pci mechanism at boot time on both the CS4630 and the south bridge.
CS4630 14 ds445pp1 3. system architectures a typical system diagram depicting connection of the CS4630 to the crystalclear cs4297/97a/98/99 ac 97 codec is given in figure 8. all analog au- dio inputs and outputs are connected to the cs4297/97a/98/99. audio data is passed between the cs4297/97a/98/99 and the CS4630 over the serial ac-link. the CS4630 provides a hardware interface for connection of a joystick and midi de- vices. a second diagram, figure 9, depicts the CS4630 supporting dual ac 97 codecs in a porta- ble design. the ac 97 interface is connected to the primary ac 97 codec in the portable and is used for all audio i/o inside and connected to the porta- ble. the ac 97 interface is sent across to the dock- ing station which contains a second ac 97 2.0/2.1 codec, used when the portable is in the docking sta- tion. software can disable the audio i/o paths on the portable that are superseded by docking station i/o and enable the paths needed in the docking sta- tion. note that both interfaces are needed in sys- tems where the cd-rom analog input is in the portable and the line in/out jacks on the docking stations are used. using the ac 97 digital link across the dock maintains the absolute highest au- dio quality along with a standard well-defined non- proprietary interface that will last through many system generations. host memory north bridge cpu south bridge cs4297 pci bus pc/pci (if used) audio out audio in figure 8. ac 97 codec interface CS4630 host memory pri. ac '97 codec north bridge cpu south bridge pci bus pc/pci (if used) audio out audio in audio accelerator card bus interface zv port bridge audio out audio in secondary pci bus portable docking station sec. ac '97 codec CS4630 figure 9. portable docking station scenario
CS4630 ds445pp1 15 4. host interface the CS4630 host interface is comprised of two sep- arate interface blocks which are memory mapped into host address space. the interface blocks can be located anywhere in the host 32-bit physical ad- dress space. the interface block locations are de- fined by the addresses programmed into the two base address registers in the pci configuration space. these base addresses are normally set up by the systems plug and play bios. the first inter- face block (located by base address 0) is a 4 kbyte register block containing general purpose configu- ration, control, and status registers for the device. the second interface block (located by base ad- dress 1) is a 1 mbyte block which maps all of the internal ram memories (sp program ram, pa- rameter ram, and sample ram) into host memo- ry space. this allows the host to directly peek and poke ram locations on the device. the relation- ship between the base address registers in the CS4630 pci configuration space and the host memory map is depicted in figure 10. the bus mastering pci bus interface complies with the pci local bus specification (version 2.1). 4.1 pci bus transactions as a target of a pci bus transaction, the CS4630 supports the memory read (from internal registers or memory), memory write (to internal registers or memory), configuration read (from CS4630 con- figuration registers), configuration write (to CS4630 configuration registers), memory read multiple (aliased to memory read), memory read line (aliased to memory read), the memory write and invalidate (aliased to memory write) transfer cycles, and i/o read, i/o write cycles (for legacy audio support). the interrupt acknowledge, spe- cial cycles, and dual address cycle transactions are not supported. as bus master, the CS4630 generates the memory read multiple, memory write, i/o read and i/o write transactions. the memory read, configura- tion read, configuration write, memory read line, memory write and invalidate, interrupt ac- 00h device id / vendor id status / command class code / revision base address register 0 base address register 1 misc. control direct i/o registers (memory mapped, 4 kbyte) direct memory interface (memory mapped, 1 mbyte) device pci config. space 04h 08h 0ch 10h 14h figure 10. host interface base address registers
CS4630 16 ds445pp1 knowledge, special cycles, and dual address cy- cle transactions are not generated. the pci bus transactions supported by the CS4630 device are summarized in table 1. note that no target abort conditions are signalled by the de- vice. byte, word, and doubleword transfers are supported for configuration space accesses. only doubleword transfers are supported for register or memory area accesses. bursting is not supported for host-initiated transfers to/from the CS4630 in- ternal register space, ram memory space, or pci configuration space (disconnect after first phase of transaction is completed). initiator target type pci dir host registers (ba0) mem write in host registers (ba0) mem read out host memories (ba1) mem write in host memories (ba1) mem read out host config space 1 config write in host config space 1 config read out host legacy h/w i/o write in host legacy h/w i/o read out cs46xx host system mem write out cs46xx host system mem read in cs46xx south bridge i/o write out cs46xx south bridge i/o read in table 1. pci interface transaction summary
CS4630 ds445pp1 17 4.2 configuration space the content and format of the pci configuration space is given in table 2. byte 3 byte 2 byte 1 byte 0 offset device id: r/o, 6003h vendor id: r/o, 1013h 00h status register, bits 15-0: bit 15 detected parity error: error bit bit 14 signalled serr: error bit bit 13 received master abort: error bit bit 12 received target abort: error bit bit 11 signalled target abort: error bit bit 10-9 devsel timing: r/o, 10b (slow) bit 8 data parity error detected: error bit bit 7 fast back to back capable: r/o 0 bit 6 user definable features: r/o 0 bit 5 66mhz bus: r/o 0 bit 4 new capabilities: r/o 1 bit 3-0reserved: r/o 0000 reset status state: 0410h write of 1 to any error bit position clears it. command register, bits 15-0: bit 15-10: reserved, r/o 0 bit 9 fast b2b enable: r/o 0 bit 8 serr enable: r/w, default 0 bit 7 wait control: r/o 0 bit 6 parity error response: r/w, default 0 bit 5 vga palette snoop: r/o 0 bit 4 mwi enable: r/o 0 bit 3 special cycles: r/o 0 bit 2 bus master enable: r/w, default 0 bit 1 memory space enable: r/w, default 0 bit 0 io space enable: r/o 0 04h class code: r/o 040100h class 04h (multimedia device), sub-class 01h (audio), interface 00h revision id: r/o 01h 08h bist: r/o 0 header type: bit 7: r/o 0 bit 6-0: r/o 0 (type 0) latency timer: bit 7-3: r/w,default 0 bit 2-0: r/o 0 cache line size: r/o 0 0ch base address register 0 device control register space, memory mapped. 4 kbyte size bit 31-12: r/w, default 0. compare address for register space accesses bit 11 - 4: r/o 0, specifies 4 kbyte size bit 3: r/o 0, not prefetchable (cacheable) bit 2-1: r/o 00, location type - anywhere in 32 bit address space bit 0: r/o 0, memory space indicator 10h base address register 1 device memory array mapped into host system memory space, 1 mbyte size bit 31-20: r/w, default 0. compare address for memory array accesses bit 19 - 4: r/o 0, specifies 1 mbyte size bit 3: r/o 0, not prefetchable (cacheable) bit 2-1: r/o 00, location type - anywhere in 32 bit address space bit 0: r/o 0, memory space indicator 14h base address register 2: r/o 00000000h, unused 18h base address register 3: r/o 00000000h, unused 1ch base address register 4: r/o 00000000h, unused 20h base address register 5: r/o 00000000h, unused 24h cardbus cis pointer: r/o 00000000h, unused 28h table 2. pci configuration space
CS4630 18 ds445pp1 subsystem id r/o defaults to 0000h if eeprom is not present, otherwise loaded from the eeprom. writable via configuration space offset 0xfeh or ba0:4b4h. subsystem vendor id r/o defaults to 0000h if eeprom is not present, otherwise loaded from the eeprom. writable via configuration space offset 0xfch or ba0:4b4h. 2ch expansion rom base address: r/o 00000000h, unused 30h reserved: r/o 00000000h 34h reserved: r/o 00000000h 38h max_lat: r/o 18h 24 x 0.25us = 6 us min_gnt: r/o 04h 4 x 0.25us = 1us interrupt pin: r/o 01h, inta used interrupt line: r/w, default 0 3ch pmc bit 15: pme# from d3cold: r/o 0(default) or 1(configurable) bit 14: pme# from d3hot: r/o 0(default) or 1(configurable) bit 13: pme# from d2: r/o 0(default) or 1(configurable) bit 12: pme# from d1: r/o 0(default) or 1(configurable) bit 11: pme# from d0: r/o 0(default) or 1(configurable) bit 10: d2 support: r/o 1 bit 9: d1 support: r/o 1 bit 8-6:aux current: r/o 000(default) or configurable bit 5: device specific init: r/o 1 bit 4: auxiliary power: r/o 0 bit 3: pme# clock: r/o 0 bit 2-0: version: r/o 010 next item pointer: r/o 0h capability id: r/o 1h 40h data: r/o 0 pmcsr_bse: r/o 0 pmcsr bit 15: pme# status: r/w 0 bit 14-13: data scale: r/o 00 bit 12-9: data select: r/o 0000 bit 8: pme_en: r/w 0 bit 7-2: reserved: r/o 000000 bit 1-0: power state: r/w 00 44h dynamic config register bit 31: pme support shadow bit: r/w 0 bit 30: reserved: r/w 0 bits 29-27: aux current shadow bits: r/o 000 bits 26-24: reserved: r/o 000 bits 23-16: dynamic cnfg bits 23-16: r/w 0h dynamic config register bits 15-0: dynamic cnfg bits 15-0: r/w 0h f8h subsystem id shadow register 0feh w/o shadow subsystem id (0x2e) subsystem vendor id shadow register 0fch w/o shadow subsystem id (0x2c) fch byte 3 byte 2 byte 1 byte 0 offset table 2. pci configuration space (cont.)
CS4630 ds445pp1 19 4.3 subsystem vendor id fields the subsystem id and subsystem vendor id con- figuration fields can be loaded in two different ways. for systems using an eeprom, typically add-in cards, the eeprom auto loads the data. for a system using bios, typically mother boards, the configuration space is loaded at offset fch (see table 2). once these values are loaded they will ap- pear in the configuration space offset 2ch. the subsystem id and subsystem vendor id fields in the pci configuration space default to value 0000h unless an external eeprom device is de- tected or unless the host has written to the appropri- ate internal register to program the values. 4.4 dynamic config register the dynamic configuration register is primarily used to configure the hardware to support the gen- eration of the pme# signal to the pci bus and store the particular hardware configuration. bit 31, pme_support shadow, shadows bits 14-11 of the configuration space pmc register at offset 42h. bits 29-27 will shadow bits 8-6 of the pmc regis- ter if the vaux_sense pin is high indicating auxil- lary power is available. otherwise, bits 8-6 will be set to 000b. bits 23-0 are general purpose read/write bits and the definitions will be deter- mined by the driver. the dynamic configuration register bits can be loaded in two different ways. for systems using an eeprom typically add-in cards, the eeprom auto loads the data. for a system using bios, typi- cally mother boards, the dynamic configuration register is loaded at offset f8h (see table 2). the dynamic configuration register bits will default to value 0000h unless an external eeprom device is detected or unless the host has written to the appro- priate internal register to program the values. 4.5 interrupt signal the CS4630 pci interface includes an interrupt controller function which receives interrupt re- quests from multiple sources within the CS4630 device, and presents a single interrupt line (inta) to the host system. interrupt control registers in the CS4630 provide the host interrupt service routine with the ability to identify the source of the inter- rupt and to clear the interrupt sources. in the CS4630, the single external interrupt is expanded by the use of virtual channels. each data stream which is read from or written to a modular buffer is assigned a virtual channel number. this virtual channel number is signalled by the dma sub- system anytime the associated modular buffer pointer passes the mid-point or wraps around. vir- tual channels are also used for message passing be- tween the CS4630 and the host.
CS4630 20 ds445pp1 5. serial port configurations a flexible serial audio interface is provided which allows connection to external analog-to-digital converters (adcs), digital-to-analog converters (dacs) or codecs (combined adc and dac functions) in several different configurations. the serial audio interface includes a primary input/out- put port with dedicated serial data pins (sdin, sd- out), two auxiliary audio output ports (sdo2, sdo3) which share pins with the joystick interface button input functions, and one auxiliary audio in- put port (sdin2). each of these digital audio input and output pins carry two channels of audio data. these two channels may comprise the left and right channels of a stereo audio signal, or two indepen- dent monaural audio signals. each digital audio channel is internally buffered through a 16 sample x 20-bit fifo. the data format for the serial digital audio ports varies depending on the configuration. the primary configuration in- cludes a CS4630 plus a cs4297/97a/98/99. the CS4630 communicates with the cs4297/97a/98/99 over the ac-link as specified in the intel? audio codec 97 specification (revi- sion 2.1). a block diagram for the ac 97 control- ler configuration is given in figure 11. in this configuration, the ac 97 codec is the timing mas- ter for the digital audio link. the asdout output supports data transmission on all ten possible sam- ple slots (output slots 3 - 12). the asdin input supports receiving of audio sample data on all input sample slots (input slots 3 - 12). the sdo2 and sdo3 serial outputs and the sdin2 serial input are not supported in this configuration. in the dual ac 97 system, the primary ac 97 codec is connected as in the single codec case; however, a second cs4297a/98/99 is connected to a completely sepa- rate serial data in pin asdin2. a block diagram abitclk async asdout asdin arst# midiin midiout jacx, jacy, jbcx, jbcy jab1, jab2, jbb1, jbb2 joystick/ midi port bit_clk sync sdata_out sdata_in reset# 24.576 mhz cs429 7a 12.288 mhz 48 khz analog interface figure 11. ac 97 codec connection diagram CS4630
CS4630 ds445pp1 21 depicting the dual ac 97 codec configuration as a docking station is given in figure 9. in this scenar- io, the first codec is used in the portable for tradi- tional functions such as analog support for the portables line in, mic in, and line out jacks. the ac link to the dock is buffered and sent across to the docking station to support a second cs4297a/98/99 that supports the docks analog jacks. when the system gets a message that the docking station is attached, the software can re- place the portables analog jack control for the docking stations jacks seemlessly. using a stan- dard ac link for the docking station support main- tains the highest quality of audio over analog docking station scenarios. in addition, since the ac link is a standard, the docking station can be uti- lized over a number of portable generations with- out concern for obsolescence. the signal connections between the CS4630 and the dual codecs are shown in figure 12. in this configuration, both ac 97 codecs run off the same abitclk with the primary ac 97 codec being the timing master for the first ac link and for the CS4630. the secondary cs4297/97a/98/99 and the CS4630 are slaves to the incoming abitclk. full fifo buffers for both codecs are supported. abitclk async asdout asdin arst# midiin midiout jacx, jacy, jbcx, jbcy jab1, jab2, jbb1, jbb2 joystick/ midi port bit_clk sync sdata_out sdata_in reset# asdin2 bit_clk sync sdata_out sdata_in reset# analog interface analog interface 24.576 mhz cs4297/97a/99 secondary ac'97 2.0 codec 12.288 mhz 48 khz figure 12. dual ac 97 codec connection diagram CS4630
CS4630 22 ds445pp1 6. game port 6.1 midi port in the ac 97 controller configuration, a bi-direc- tional midi interface is provided to allow connec- tion of external midi devices. the midi interface includes 16-byte fifos for the midi transmit and receive paths. 6.2 joystick port in the ac 97 controller configuration, a joystick port is provided. the joystick port supports four coordinate channels and four button channels. the coordinate channels provide joystick position- al information to the host, and the button channels provide user button event information. the joystick interface is capable of operating in the traditional polled mode, but also provides a hardware ac- celerated mode of operation wherein internal counters are provided to assist the host with coordi- nate position determination. the joystick schemat- ic is illustrated in figure 13. +5 v 1 9 8 4 5 2 7 1nf 3 6 1nf 5.6 nf 2.2 k w 2.2 k w 2.2 k w 2.2 k w 4.7 k w 5.6 nf 5.6 nf 5.6 nf 10 11 12 13 14 15 4.7 k w 4.7 k w 4.7 k w 4.7 k w jab1 jbb1 jacx jbcx jbcy jacy jbb2 jab2 midiout midiin 1nf 1nf dsp figure 13. joystick logic
CS4630 ds445pp1 23 7. eeprom interface the eeprom configuration interface allows the connection of an optional external eeprom de- vice to provide power-up configuration informa- tion. the external eeprom is not required for proper operation; however, in some applications power-up configuration settings other than the de- fault values may be required to support specific op- erating system compatibility requirements. after a hardware reset, an internal state machine in the CS4630 will automatically detect the presence of an external eeprom device (assuming eepdis is low) and load the subsystem id and subsystem vendor id fields, along with two bytes of general configuration information, into internal registers. at power-up, the CS4630 will attempt to read from the external device, and will check the data re- ceived from the device for a valid signature header. if the header data is invalid, the data transfer is aborted. after power-up, the host can read or write from/to the eeprom device by accessing specific registers in the CS4630. cirrus logic provides soft- ware to read and write the eeprom. the two-wire interface for the optional external eeprom device is depicted in figure 14. during data transfers, the data line (eedat) can change state only while the clock signal (eeclk) is low. a state change of the data line while the clock sig- nal is high indicates a start or stop condition to the eeprom device. the eeprom device read access sequence is shown in the figure 15. the timing follows that of a random read sequence. the CS4630 first per- forms a dummy write operation, then generates a start condition followed by the slave device address and the byte address of zero. the CS4630 always begins access at byte address zero and continues access a byte at a time, using a sequential read, until all needed bytes in the eeprom are read. since only a maximum of 12 bytes are needed, the small- est eeprom available will suffice. slimd sp core eedat eeclk 4.7 k w 2-wire serial eeprom figure 14. external eeprom connection s10100000a00000000as10100001a data data p 1 a start part address start acknowledge no acknowledge stop acknowledge data eeprom write read bank address part address cs46xx figure 15. eeprom read sequence
CS4630 24 ds445pp1 8. general purpose i/o pins many of the CS4630 signal pins are internally mul- tiplexed to serve different functions depending on the environment in which the device is being used. several of the CS4630 signal pins may be used as general purpose i/o pins when not required for oth- er specific functions in a given application. 8.1 egpio in addition to the gpio pins on the CS4630, ex- tended general purpose i/o has been added. four egpio pins are not multiplexed, egpio[7, 2:0]; whereas; egpio[6:3] are shared with the asyn- chronous serial port. when this second async. seri- al port is not used, all the egpio pins are available. these pins have extended functionality in that any egpio pin can be programmed to cause a power management wake-up event on the pme# signal. these pins also can be programmed as: ? input or output, ? edge or level sensitive (sticky), ? active high or low input, ? cmos or open-drain output 9. zv port serial interface the zv port interface consists of three input pins: zlrck, zsclk, and zsdata. zlrck is the left/right clock indicating which channel is currently being received. zsclk is the serial bit clock where zlrck and zsdata change on the falling edge and serial data is internally latched on the rising edge. note that the serial data starts one zsclk period after zlrck transitions. figure 16 illustrates the clocking on the zv port pins. 10. consumer iec-958 digital interface (s/pdif) the CS4630 supports the industry standard iec- 958 consumer digital interface. sometimes this standard is referred to as s/pdif, which refers to an older version of this standard. this output provides an interface, external to the pc, for storing digital audio (as in a dat or recordable cd-rom) or playing digital audio from digital speakers. figure 17 illustrates the circuit necessary for imple- mentation of the iec-958 consumer interface. an external buffer is required to drive the current needed for the 75 w interface. a current driver is implemented to increase the transmission range of the coaxial circuitry. figure 18 illustrates an optional fiber optic circuit. the optical circuit connects directly to the CS4630 and no additional current driver is needed. zlrck zsclk left channel right channel zsdata 6 54 3 210 98 7 15 14 13 12 11 10 654 32 10 9 87 15 14 13 12 11 10 figure 16. zv port clocking format
CS4630 ds445pp1 25 dgnd dgnd dgnd dgnd 1 2 1 2 374 90.9 1 5 4 8 1 2 j-rca-ra-pcb gnd vcc 1 2 4 5 +5 v pci 0.1 m f sn75179d spdif i 3 spdifo 6 7 8 iec_958_tx 29398 dgnd 1 2 iec_958_rx j-rca-ra-pcb 1 2 75 0.1 m f 0.1 m f 21 figure 17. iec consumer interface implementation circuit dgn d dgnd dgnd +5v_pci spdifo totx-173 1 2 3 4 5 6 8.2k .1 m f 5 6 dgnd dgnd totx-173 dgnd +5v_pci spdifi 47 h 1 f 1 k 4 3 2 1 figure 18. optional fiber optic circuit
CS4630 26 ds445pp1 11. pci power management the CS4630 supports the pci bus power manage- ment interface specification (version 1.1). the CS4630 supports all power states and is capable of pme# generation from d0 - d3 hot , and d3 cold pro- vided auxillary 3.3v power is available the pci power management specification defines four major power states: d0 (fully on), d1, d2, and d3 (fully off). the d3 state is divided into two sub- states, d3hot and d3cold. d3cold differs from d3hot in that the normal pci bus vcc power sourc- es are turned off. 11.1 d0 state the d0 state is divided into two substates, d0active and d0uninitialized. the d0unitialized state describes a device that has just received a pci rst# signal and has not yet been programmed; therefore, it is not consuming full power. the d0active state describes a device that has been pro- grammed and is fully operational. the CS4630 must initially be put into d0 before being used. upon entering d0 from power on reset, or transition from d3cold, the CS4630 will be in an uninitialized state. once initialized by the system software, it will transition to the d0active state. CS4630 operation during d0 state: ? phase lock loop - running ? sp clock - running ? sp ram clock - running ? ac link - running 11.2 dl state dl is used as a light sleep state. all necessary inter- nal state information and data samples are pre- served while in d1. the transition back to d0 state will occur within 100ms. CS4630 operation during d1 state: ? phase lock loop - running ? sp clock - stopped ? sp ram clock - running ? ac link - running 11.3 d2 state this state requires significant power savings while still retaining the abi1ity to recover to a previous condition. the transition back to d0 state will oc- cur within 100ms. CS4630 operation during d2 state: ? phase lock loop - running ? sp clock - stopped ? sp ram clock - stopped ? ac link - running 11.4 d3 hot state in this state, function context need not be main- tained. when the CS4630 is brought back to d0 (the only legal state transition from d3), software will perform a full reinitialization of the CS4630 including its pci configuration space.when pro- grammed to d0 from d3, the CS4630 performs the equivalent of a warm reset and returns to the d0uninitialized state without pci rst# being as- serted. CS4630 operation during d3hot state: ? phase lock loop - stopped ? sp clock - stopped ? sp ram clock - stopped ? ac link - stopped 11.5 d3 cold state when vcc is removed from the pci bus and pci rst# is asserted, the CS4630 will transition imme- diately to d3cold. when power is restored, pci rst# will be de-asserted and the CS4630 will re- turn to d0uninitialized state with a full pci 2.1 compliant power on reset sequence whenever pme# has not been enabled. if the CS4630 is enabled to generate a pme# event from the d3 power state, and an auxillary 3.3 v power source is available, no logic within the chip will be reset during the assertion of pci rst# while the main system 3.3 v is removed. CS4630 operation during d3cold state: ? phase lock loop - stopped
CS4630 ds445pp1 27 ? sp clock - stopped ? sp ram clock - stopped ? ac link - stopped 11.6 CS4630 pme# assertion two methods are supported by the CS4630 in gen- erating a pme# event to the pci bus. method one, with abitclk running, is primarily used when the sp is required to perform a processing task such as discriminating a valid ring condition from the daa or decode incoming caller-id information. the other method is used when maximum power savings is required (both abitclk and pci clk are off) and the sp is not needed for signal process- ing. 11.6.1 abitclk on the CS4630, with abitclk running, can assert pme# from the d0, d1, d2, d3hot and d3cold power management device states in response to software executing on the sp. the CS4630 sp and logic that generates this inter- nal event and asserts pme# is clocked from the ac 97 abitclk signal when connected to an ac 97 codec. while in this mode, the ac link is not al- lowed to be powered down by setting the pr4 bit the ac 97 codec. abitclk must be allowed to run. CS4630 operation with pme# generation enabled and abitclk running: ? phase lock loop - running at reduced rate ? sp clock - running at reduced rate ? sp ram clock - running at reduced rate ? ac link - running 11.6.2 abitclk off due to the short recovery times from d1 and d2 power states, the CS4630 will only support asser- tion of pme# from the d3hot and d3cold power management device states while the codec is in pr4 power state with abitclk off. with abit- clk off, the CS4630 will generate a pme# event in response to a low-to-high transition on the as- din or asdin2 pin when the CS4630 is config- ured for ac 97 operation and the ac link is down (codec in pr4). codecs compliant with the ac 97 2.0 specification use this mechanism to signal a wake-up event to the ac 97 controller. CS4630 operation with pme# generation enabled and abitclk stopped ? phase lock loop - stopped ? sp clock - stopped ? sp ram clock - stopped ? ac link - stopped 11.7 on card vaux switching logic three new signal i/o are required for support of pme generation from d3cold on the CS4630 de- vice. vaux_sense is an input pin used by the pci configuration registers to determine if 3.3 vaux is present on the pci bus. the signal level on this pin determines the value presented in the power man- agement capabilities register at offset 0x42. vaux_sense will contain an internal pull-down re- sistor to maintain backwards compatibility. pcivdd_sense is an input pin used to sense the main system 3.3 v to determine when d3 cold pow- er state has begun and to block the pci rst# signal from causing a reset condition to critical logic. pcivdd_sense will contain an internal pull-down resistor to maintain backwards compatibility. an output pin, vaux_sel, is used to control external power mosfet transistors which switch the CS4630s voltage supply from main 3.3 vcc to 3.3 vaux. if 3.3 vaux is used to supply power during d3cold and vdd5ref is tied to +5 v, then a low v f schottky diode, similar to a standard bat54 de- vice, is required to be placed in series with the vdd5ref signal. no diode is require if vdd5ref is tied to 3.3 vaux.
CS4630 28 ds445pp1 10uf vaux_sel +3.3v_main +3.3v_aux +3.3vd vaux_sense pcivdd_sense to pcivdd pins 3.3v to 2.5v ldo vreg to cvdd pins 3.3k 2k 470 470 figure 19. on-card 3.3vaux switching logic
CS4630 ds445pp1 29 12. pin description egpio[3]/asclk 103 egpio[4]/asfclk 104 egpio[5]/asdi 105 egpio[6]/asdo 106 asdin2 107 pme# 108 inta# 109 rst# 110 pciclk 111 gnt# 112 req# 113 pcivdd[0] 114 pcignd[0] 115 ad[31] 116 ad[30] 117 ad[29] 118 ad[28] 119 ad[27] 120 pcignd[1] 121 pcivdd[1] 122 ad[26] 123 ad[25] 124 ad[24] 125 c/be[3]# 126 idsel 127 pcivdd[2] 128 test 65 jacx 66 jacy 67 jbcx 68 jbcy 69 jab1/sdo2 70 jab2/sdo3 71 jbb1/lrclk 72 jbb2/mclk 73 midiin 74 pcivdd[8] 75 pcignd[8] 76 midiout 77 cvdd[2] 78 cgnd[2] 79 zlrclk 80 zsclk 81 zsdata 82 spdifi 83 spdifo 84 egpio[0] 85 egpio[1] 86 egpio[2] 87 sdin2/gpio 88 cgnd[3] 89 cvdd[3] 90 cryvdd 91 volup/xtali 92 voldn/xtalo 93 crygnd 94 vdd5ref 95 abitclk/sclk 96 asdout/sdout 97 asdin/sdin 98 async/fsync 99 arst# 100 eeclk/pcreq# 101 eedat/pcgnt# 102 38 pcignd[5] 37 ad[14] 36 ad[15] 35 c/be[1]# 34 par 33 serr# 32 perr# 31 stop# 30 pcignd[4] 29 pcivdd[4] 28 devsel# 27 cvdd[0] 26 cgnd[0] 25 trdy# 24 irdy# 23 eepdis 22 vaux_sense 21 pcivdd_sense 20 nc 19 nc 18 nc 17 nc 16 vaux_sel 15 frame# 14 c/be[2]# 13 cgnd[1] 12 cvdd[1] 11 ad[16] 10 ad[17] 9ad[18] 8 pcivdd[3] 7 pcignd[3] 6ad[19] 5ad[20] 4ad[21] 3ad[22] 2ad[23] 1 pcignd[2] 64 clkrun# 63 egpio[7] 62 arst2# 61 async2 60 asdout2 59 abitclk2 58 pcivdd[7] 57 pcignd[7] 56 ad[0] 55 ad[1] 54 ad[2] 53 ad[3] 52 ad[4] 51 ad[5] 50 ad[6] 49 ad[7] 48 pcignd[6] 47 pcivdd[6] 46 c/be[0]# 45 ad[8] 44 ad[9] 43 ad[10] 42 ad[11] 41 ad[12] 40 ad[13] 39 pcivdd[5] 128-pin mqfp CS4630-cm
CS4630 30 ds445pp1 12.1 pci interface ad[31:0] - address / data bus, i/o these pins form the multiplexed address/data bus for the pci interface. c/be[3:0]# - command type / byte enables, i/o these four pins are the multiplexed command/byte enables for the pci interface. during the address phase of a transaction, these pins indicate cycle type. during the data phases of a transaction, active low byte enable information for the current data phase is indicated. these pins are inputs during slave operation and they are outputs during bus mastering operation. par - parity, i/o, active high the parity pin indicates even parity across ad[31:0] and c_be[3:0] for both address and data phases. the signal is delayed one pci clock from either the address or data phase for which parity is generated. frame# - cycle frame, i/o, active low frame# is driven by the current pci bus master to indicate the beginning and duration of a transaction. irdy# - initiator ready, i/o, active low irdy# is driven by the current pci bus master to indicate that as the initiator it is ready to transmit or receive data (complete the current data phase). trdy# - target ready, i/o, active low trdy# is driven by the current pci bus target to indicate that as the target device it is ready to transmit or receive data (complete the current data phase). stop# - transition stop, i/o, active low stop# is driven active by the current pci bus target to indicate a request to the master to stop the current transaction. idsel - initialize device select, input, active high idsel is used as a chip select during pci configuration read and write cycles. devsel# - device select, i/o, active low devsel# is driven by the pci bus target device to indicate that it has decoded the address of the current transaction as its own chip select range. req# - master request, three-state output, active low req# indicates to the system arbiter that this device is requesting access to the pci bus. this pin is high-impedance when rst# is active.
CS4630 ds445pp1 31 gnt# - master grant, input, active low gnt# is driven by the system arbiter to indicate to the device that the pci bus has been granted. perr# - parity error, i/o, active low perr# is used for reporting data parity errors on the pci bus. serr# - system error, open drain output, active low serr# is used for reporting address parity errors and other catastrophic system errors. inta# - host interrupt a (for sp), open drain output, active low inta# is the level triggered interrupt pin dedicated to servicing internal device interrupt sources. pciclk - pci bus clock, input pciclk is the pci bus clock for timing all pci transactions. all pci synchronous signals are generated and sampled relative to the rising edge of this clock. rst# - pci device reset, active low rst# is the pci bus master reset. vdd5ref: clean 5 v (or 3.3 v) power supply vdd5ref is the power connection pin for the 5 v pci pseudo supply for the pci bus drivers. this pin enables the pci interface to support and be tolerant of 5 volt signals. it must be connected to +5 volts. if the system pci bus is known to support only +3.3 v signal levels, then this pin can be connected to +3.3 v or +3.3 v_aux when supporting pme generation from d3cold. pcivdd[8:0] - pci bus driver power supply pcivdd pins are the pci driver power supply pins. these pins must have a nominal +3.3 volts. pcignd[8:0] - pci bus driver ground pins pcignd pins are the pci driver ground reference pins. 12.2 pci power management interface pins pme# - pci power management event, open drain output, active low pme# signals a power management event. this signal can go low because of an ac 97 2.0 codec or sp software.
CS4630 32 ds445pp1 vaux_sel - select 3.3 vaux, output, active high this pin is used to switch the on-card power mosfets to support 3.3 vaux supply when implementing pme# generation from d3 cold power management state. pcivdd_sense - sense main system 3.3 v, input, active high, weak internal pulldown this pin is used to determine the presence of the main 3.3 v supply. this signal is used in implementing pme# generation from d3 cold power management state. if not used, leave un- connected. vaux_sense - sense 3.3 vaux, input, active high, weak internal pulldown this pin is used to determine the presence of the auxiliary 3.3 vaux supply. this signal is used in implementing pme# generation from d3 cold power management state. if not used, leave un- connected. 12.3 external interface pins test - test mode strap, input, active high this pin is sampled at reset for test mode entry. if it is high at reset, test mode is enabled. this pin must be pulled to ground for normal operation. eedat/pcgnt# - eeprom data line / pc/pci grant, i/o for add-in card designs, this is the data line for external serial eeprom containing device configuration data. when used with an external eeprom (eepdis must be low), a 4.7 k w pullup resistor is required. in motherboard designs using pc/pci, this pin is the pc/pci serialized grant input. in designs with neither of the above requirements, this pin can be used as a general purpose input or open drain output (gpio2). eeclk/pcreq# - eeprom clock line / pc/pci request, output for add-in card designs, this is the clock line for external serial eeprom containing device configuration data (eepdis must be low). in motherboard designs using pc/pci, this pin is the pc/pci serialized request output. in designs with neither of the above requirements, this pin can be used as a general purpose output pin (gpout). eepdis - eeprom disable, input, active high this strapping pin, when tied high, disables the eeprom interface. when low, the CS4630 checks at power-up for an external eeprom on the eeclk and eedat pins. sdin2/gpio - serial data input 2 / general purpose i/o pin, i/o this dual function pin defaults as a general purpose i/o pin. in non-ac 97 system configurations, this pin can function as a second stereo digital data input pin if enabled.
CS4630 ds445pp1 33 volup/xtali - volume-up button / crystal in, input this dual function pin is either the volume-up button control input or the crystal oscillator input pin, depending on system configuration. this pin may also be used as a general purpose input if its primary function is not needed. voldn/xtalo - volume-down button / crystal output, i/o this dual function pin is either the volume-down button control input or the crystal oscillator output pin, depending on system configuration. this pin may also be used as a general purpose input if its primary function is not needed. 12.4 clock / miscellaneous clkrun# - optional system clock control, open drain output, active low clkrun# is an optional pci signal defined for mobile operations. this is a bidirectional pin indicating that the pci clock is required. this signal pin is not available on the add-in card connector. cryvdd - crystal & pll power supply power pin for crystal oscillator and internal phase locked loop. this pin must be connected to a nominal +3.3 volts. crygnd - crystal & pll ground supply ground pin for crystal oscillator and internal phase locked loop. jacx, jacy, jbcx, jbcy - joystick a and b x/y coordinates, i/o these pins are the 4 axis coordinates for the joystick port. these pins may also be used as general purpose inputs or open drain outputs if their primary function is not needed. jab1/sdo2 - joystick a button 1 / serial data output 2, i/o this dual function pin defaults as jab1 (button 1 input for joystick a). in non-ac 97 system configurations, this pin can function as a second stereo digital data output pin if enabled. this pin can also be a general purpose polled input if a second data output stream is not required. jab2/sdo3 - joystick a button 2 / serial data output 3, i/o this dual function pin defaults as jab2 (button 2 input for joystick a). in non-ac 97 system configurations, this pin can function as a third stereo digital data output pin if enabled. this pin can also be a general purpose polled input if a third data output stream is not required. jbb1/lrclk - joystick b button 1 / l/r framing clock, i/o this dual function pin defaults as jbb1 (button 1 input for joystick b). in non-ac 97 system configurations, this pin can function as a left/right framing clock output pin for sdo2 and sdo3. this pin can also be used as a general purpose polled input if alternate data output streams are not required.
CS4630 34 ds445pp1 jbb2/mclk - joystick b button 2 / master clock, i/o this dual function pin defaults as jbb2 (button 2 input for joystick b). in non-ac 97 system configurations, this pin can function as a master (256x sample rate) output clock if enabled. this pin can also be used as a general purpose polled input if alternate data output streams are not required. midiin - midi data input this is the serial input pin for the internal midi port. midiout - midi data output this is the serial output pin for the internal midi port. cvdd[3:0] - core power supply core/stream processor power pins. these pins must be connected to a nominal +2.5 volts. cgnd[3:0] - core ground supply core/stream processor ground reference pins. nc - no connect do not connect any signal to this pin. 12.5 serial codec interface abitclk/sclk - primary ac 97 bit clock / serial audio data clock, i/o master timing clock for serial audio data. in ac 97 configurations, this pin is an input which drives the timing for the ac 97 interface, along with providing the source clock for the cs46 30 . in external dac configurations, its an output, providing the serial bit clock. async/fsync - primary ac 97 frame sync / serial audio frame sync, i/o framing clock for serial audio data. in ac 97 configurations, this pin is an output which indicates the framing for the ac 97 link. in external dac configurations, this pin is an fsync output, providing the left/right framing clock. asdout/sdout - primary ac 97 data out / serial audio data out, output ac 97 serial data out/serial audio output data. arst# - primary ac 97 reset, output, active low ac 97 link reset pin. this pin also functions as a general purpose reset output in non-ac 97 configurations and will follow rst# to ground, but must be forced high by software. asdin/sdin - primary ac 97 data in / serial audio data in, input, weak internal pulldown ac 97 (2.1) serial audio input data for the primary ac 97 codec
CS4630 ds445pp1 35 asdin2 - second ac 97 data in, input, weak internal pulldown ac 97 (2.1) serial audio input data for the second ac 97 codec. the other ac link pins are either shared with the first ac 97 interface or connected to the second complete ac 97 interface listed below. abitclk2 - second ac 97 link bit clock, input, weak internal pulldown master timing clock for the second ac 97 serial link. async2 - second ac 97 link frame sync, output framing clock for second ac 97 link serial audio data. this pin is an output which indicates the framing for the second ac 97 link. asdout2 - second ac 97 link data out, output ac 97 serial data out/serial audio output data. arst2# - second ac 97 link reset, output, active low second ac 97 link reset pin. this pin also functions as a general purpose reset output in non- ac 97 configurations and will follow rst# to ground, but must be forced high by software. 12.6 zv port serial interface zsclk - zv port serial clock, input, weak internal pulldown zv port serial bit clock. zlrclk - zv port left/right clock, input, weak internal pulldown zv port left/right channel delineation. zsdata - zv port serial data in, input, weak internal pulldown zv port serial data input pin. 12.7 consumer digital audio i/o (s/pdif) spdifo - consumer digital audio out, output this cmos pin outputs serial data that conforms to the iec-958 consumer format. the data is bi-phase mark encoded and requires external drivers. spdifi - consumer digital audio in, input, weak internal pulldown this pin receives asynchronous serial data that conforms to the iec-958 consumer format. the data should be bi-phase mark encoded.
CS4630 36 ds445pp1 12.8 asynchronous serial interface and enhanced general purpose i/o asclk/egpio[3] - async. serial port clock / enhanced gen. purpose i/o, i/o serial clock that controls the asynchronous serial interface. as asclk, this pin can be either an asynchronous input bit clock or, when the ac 97 interface is enabled, can be an output programmed for a frequency of abitclk/4. when not used as an asynchronous port bit clock, this pin is enhanced general purpose i/o bit 3 (see egpio[7, 2:0] for more details). asfclk/egpio[4] - async. serial frame clock / enhanced gen. purpose i/o, i/o serial frame signal that delineates left from right data. as asflck, this pin can be either an input l/r framing clock that must be synchronous to asclk, or when the ac 97 interface is enabled, an output fixed at asclk/64. when not used as an asynchronous port framing signal, this pin is enhanced general purpose i/o bit 4 (see egpio[7, 2:0] for more details). asdi/egpio[5] - async. serial port data in / enhanced gen. purpose i/o, i/o when used as asdi, stereo data is clocked with asclk with asfclk delineating left from right. otherwise, this pin is enhanced general purpose i/o bit 5 (see egpio[7, 2:0] for more details). asdo/egpio[6] - async. serial port data out / enhanced gen. purpose i/o, i/o when used as asdo, stereo data is clocked using asclk with asfclk delineating left from right. otherwise, this pin is enhanced general purpose i/o bit 6 (see egpio[7, 2:0] for more details). egpio[7, 2:0] - extended general purpose i/o bits, i/o these bits along with bits egpio[6:3] have extended programmability and can be used for any application such as modem daa control. programmability features include: direction, polarity, level/edge and sensitive.
CS4630 ds445pp1 37 13. package outline inches millimeters dim min max min max a --- 0.134 --- 3.400 a1 0.010 --- 0.250 --- b 0.007 0.011 0.170 0.270 d 0.669 0.685 17.000 17.400 d1 0.547 0.555 13.900 14.100 e 0.906 0.921 23.000 23.400 e1 0.783 0.791 19.900 20.100 e* 0.016 0.024 0.400 0.600 0.000 7.000 0.00 7.00 l 0.029 0.041 0.730 1.030 * nominal pin pitch is 0.50 mm controlling dimension is mm. jedec designation: ms022 128l mqfp package drawing e1 e d1 d 1 e l b a1 a

▲Up To Search▲

Price & Availability of CS4630

	To Download CS4630 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .